{"product_id":"9780071445641","title":"Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification","description":"\u003cp\u003eLEARN VERILOG DESIGN WITH A MASTER\u003c\/p\u003e\u003cp\u003eThis rigorous tutorial shows electronics designers and students how to apply Verilog in sophisticated digital systems design, using over a hundred skill-building, fully worked-out, and simulated examples. Completely updated, the second edition covers Verilog 2001, new synthesis standards, testing and testbench developments, and the new OVL verification library. You'll find out just what's involved in using Verilog hardware description language (HDL) in digital system design. HDL expert Zain Navabi explains the design process in logical sequence — the way it's done in the real world.\u003c\/p\u003e\u003cp\u003eMoving from simple concepts to the more complex, Navabi interprets Verilog constructs related to design stages and design abstractions, including behavioral description, dataflow description, and structure description. With emphasis on the concepts of concurrency and delay in hardware, the text helps you grasp the essence of HDLs. Clear specification of learning objectives at the beginning of each chapter and end-of-chapter problems focus attention on key concepts.\u003c\/p\u003e\u003cp\u003eIf mastery of design with Verilog is the goal, Zain Navabi's \u003ci\u003eVerilog Digital System Design\u003c\/i\u003e is the tool.\u003c\/p\u003e\u003cp\u003eMUST-HAVE CD INCLUDED:\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eVerilog and VHDL simulators \u003c\/li\u003e\n\u003cli\u003eSynthesis tools \u003c\/li\u003e\n\u003cli\u003eMixed-level logic and Verilog design environment \u003c\/li\u003e\n\u003cli\u003eFPGA design tools and environments from Altera \u003c\/li\u003e\n\u003cli\u003eRelated tutorials and standards \u003c\/li\u003e\n\u003cli\u003eAll worked examples from the book, including testbench and simulation-run reports for every example \u003c\/li\u003e\n\u003cli\u003eComplete CPU examples with Verilog code and software tools \u003c\/li\u003e\n\u003cli\u003eOVL verification libraries and tutorials\u003c\/li\u003e\n\u003c\/ul\u003e\u003cp\u003eTHE BEST VERILOG TUTORIAL — UPDATED:\u003c\/p\u003e\u003cp\u003e\u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eVerilog 2001, step by step in examples and text \u003c\/li\u003e\n\u003cli\u003eOVL verification library \u003c\/li\u003e\n\u003cli\u003eNew synthesis standards \u003c\/li\u003e\n\u003cli\u003eNew chapter on testbench development and verification \u003c\/li\u003e\n\u003cli\u003eProblem set in each chapter encourages review and test of key concepts \u003c\/li\u003e\n\u003cli\u003eInstructor's manual and lecture slides available for class use\u003c\/li\u003e\n\u003c\/ul\u003e\u003cp\u003eZainalabedin Navabi (Boston, MA) is Professor of Electrical and Computer Engineering at Northeastern University. He is the author of \u003ci\u003eVerilog Digital System Design.\u003c\/i\u003e\u003c\/p\u003e","brand":"McGraw-Hill Companies, The","offers":[{"title":"Default Title","offer_id":47010344763632,"sku":"9780071445641","price":89.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0737\/7593\/9824\/files\/9780071445641_p0.jpg?v=1763634925","url":"https:\/\/shop-qa.barnesandnoble.com\/products\/9780071445641","provider":"Barnes \u0026 Noble (DEV)","version":"1.0","type":"link"}