{"product_id":"9780080475929","title":"ASIC and FPGA Verification: A Guide to Component Modeling","description":"Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL\/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. \u003cbr\u003e\u003cbr\u003eASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.\u003cbr\u003e\u003cbr\u003e*Provides numerous models and a clearly defined methodology for performing board-level simulation.\u003cbr\u003e*Covers the details of modeling for verification of both logic and timing. \u003cbr\u003e*First book to collect and teach techniques for using VHDL to model \"off-the-shelf\" or \"IP\" digital components for use in FPGA and board-level design verification.","brand":"Elsevier Science","offers":[{"title":"Default Title","offer_id":47119643705584,"sku":"9780080475929","price":70.95,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0737\/7593\/9824\/files\/9780080475929_p0.jpg?v=1763637658","url":"https:\/\/shop-qa.barnesandnoble.com\/products\/9780080475929","provider":"Barnes \u0026 Noble (DEV)","version":"1.0","type":"link"}