{"product_id":"9780132441988","title":"Engineering the Complex SOC (Prentice Hall Modern Semiconductor Design Series): Fast, Flexible Design with Configurable Processors","description":"\u003cp\u003e \u003cb\u003eEngineering the Complex SOC \u003c\/b\u003e  \u003c\/p\u003e\u003cp\u003e \u003cb\u003eThe first unified hardware\/software guide to processor-centric SOC design \u003c\/b\u003e \u003c\/p\u003e  \u003cp\u003eProcessor-centric approaches enable SOC designers to complete far larger projects in far less time. Engineering the Complex SOCis a comprehensive, example-driven guide to creating designs with configurable, extensible processors. Drawing upon Tensilica’s Xtensa architecture and TIE language, Dr. Chris Rowen systematically illuminates the issues, opportunities, and challenges of processor-centric design. \u003c\/p\u003e  \u003cp\u003eRowen introduces a radically new design methodology, then covers its essential techniques: processor configuration, extension, hardware\/software co-generation, multiple processor partitioning\/communication, and more. Coverage includes: \u003c\/p\u003e  \u003cul\u003e  \u003cli\u003e  \u003cp\u003eWhy extensible processors are necessary: shortcomings of current design methods\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eComparing extensible processors to traditional processors and hardwired logic\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eExtensible processor architecture and mechanisms of processor extensibility\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eLatency, throughput, coordination of parallel functions, hardware interconnect options, management of design complexity, and other issues\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eMultiple-processor SOC architecture for embedded systems\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eTask design from the viewpoints of software andhardware developers\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eAdvanced techniques: implementing complex state machines, task-to-task synchronization, power optimization, and more\u003c\/p\u003e  \u003c\/li\u003e\n\u003cli\u003e  \u003cp\u003eToward a “sea of processors”: Long-term trends in SOC design and semiconductor technology\u003c\/p\u003e \u003c\/li\u003e \u003c\/ul\u003e  \u003cp\u003eFor all architects, hardware engineers, software designers, and SOC program managers involved with complex SOC design; and for all managers investing in SOC designs, platforms, processors, or expertise.\u003c\/p\u003e  \u003cp\u003ePRENTICE HALL\u003cbr\u003eProfessional Technical Reference\u003cbr\u003eUpper Saddle River, NJ 07458\u003cbr\u003e www.phptr.com \u003c\/p\u003e  \u003cp\u003e \u003c\/p\u003e","brand":"Pearson Education","offers":[{"title":"Default Title","offer_id":47077391663344,"sku":"9780132441988","price":69.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0737\/7593\/9824\/files\/9780132441988_p0.jpg?v=1763640279","url":"https:\/\/shop-qa.barnesandnoble.com\/products\/9780132441988","provider":"Barnes \u0026 Noble (DEV)","version":"1.0","type":"link"}