{"product_id":"9781430259275","title":"Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers","description":"\u003cp\u003e    \u003c\/p\u003e\u003cp\u003e\u003ci\u003eIntel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers\u003c\/i\u003e provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor. \u003c\/p\u003e  \u003cp\u003eXeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them. \u003c\/p\u003e  \u003cp\u003eIn this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.\u003c\/p\u003e           What you’ll learn\u003cp\u003e \u003c\/p\u003e  \u003cul\u003e   \u003cli\u003eHow to calculate theoretical Gigaflops and bandwidth numbers on the hardware and measure them through code segment \u003c\/li\u003e   \u003cli\u003eHow to estimate latencies in fetching data from different cache hierarchies, including memory subsystems \u003c\/li\u003e   \u003cli\u003eHow to measure PCIe bus bandwidth between the host and coprocessor \u003c\/li\u003e   \u003cli\u003eHow to exploit power management and reliability features built into the hardware \u003c\/li\u003e   \u003cli\u003eHow to select and manipulate the best tools to tune particular Xeon Phi applications \u003c\/li\u003e   \u003cli\u003eAlgorithms and data structures for optimizing Xeon Phi performance \u003c\/li\u003e   \u003cli\u003eCase studies of real-world Xeon Phi technical computing applications in molecular dynamics and financial simulations \u003c\/li\u003e  \u003c\/ul\u003e    \u003cp\u003e \u003c\/p\u003e  \u003cp\u003e \u003c\/p\u003e  Who this book is for      \u003cp\u003e     \u003c\/p\u003e\u003cp\u003eThis book is for developers wishing to design and develop technical computing applications to achieve the highest performance available in the Intel Xeon Phi coprocessor hardware. It provides a solid base on the coprocessor architecture, as well as algorithm and data structure case studies for Xeon Phi coprocessor. The book may also be of interest to students and practitioners in computer engineering as a case study for massively parallel core microarchitecture of modern day processors.\u003c\/p\u003e             Table of Contents\u003cp\u003e1.  Introduction to Xeon Phi Architecture \u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  2.  Programming Xeon Phi\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  3.  Xeon Phi Vector Architecture and Instruction Set\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  4.  Xeon Phi Core Microarchitecture\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  5.  Xeon Phi Cache and Memory Subsystem\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  6.  Xeon Phi PCIe Bus Data Transfer and Power Management\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  7.  Xeon Phi System Software\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  8.  Xeon Phi Application Development Tools\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  9.  Xeon Phi Application Design and Implementation Considerations\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  10.  Application Performance Tuning on Xeon Phi\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  11.  Algorithms and Data Structures for Xeon Phi\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  12.  Xeon Phi Application Development on Windows OS\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  13.  OpenCL on Intel\u003c\/p\u003e\u003cp\u003e  \u003c\/p\u003e\u003cp\u003e  14.  Shared Memory Programming on Intel Xeon Phi\u003c\/p\u003e  \u003cp\u003e \u003c\/p\u003e","brand":"Apress","offers":[{"title":"Default Title","offer_id":47122443927792,"sku":"9781430259275","price":0.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0737\/7593\/9824\/files\/9781430259275_p0.jpg?v=1763751199","url":"https:\/\/shop-qa.barnesandnoble.com\/products\/9781430259275","provider":"Barnes \u0026 Noble (DEV)","version":"1.0","type":"link"}