{"product_id":"9781849199995","title":"Nano-CMOS and Post-CMOS Electronics","description":"\u003cp\u003eContinuing from volume 1, this volume outlines circuit- and system-level design approaches and issues for these devices.\u003c\/p\u003e\u003cp\u003eTopics covered include self-healing analog\/RF circuits; on-chip gate delay variability measurement in scaled technology; FinFET SRAM circuits; nanoscale FinFET devices for PVT aware SRAM; low leakage variability aware CMOS logic circuits; thermal effects in MWCNT VLSI interconnects; an accurate PVT-aware statistical logic library for nano-CMOS integrated circuits; SPICEless RTL design optimization of nano-electronic digital integrated circuits; power-delay trade-off driven optimal scheduling of CDFGs during high level synthesis; green on-chip inductors for three-dimensional integrated circuits; 3D NoC — a promising alternative for tomorrow’s nano-system design; and DNA computing.\u003c\/p\u003e","brand":"The Institution of Engineering and Technology","offers":[{"title":"Default Title","offer_id":47038220566768,"sku":"9781849199995","price":150.0,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0737\/7593\/9824\/files\/9781849199995_p0.jpg?v=1763753339","url":"https:\/\/shop-qa.barnesandnoble.com\/products\/9781849199995","provider":"Barnes \u0026 Noble (DEV)","version":"1.0","type":"link"}